B.E. Electronics & Comm. Engg:VLSI CAD

Thapar University
In Patiala

Price on request
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Important information

Typology Bachelor
Start Patiala
Duration 4 Years
  • Bachelor
  • Patiala
  • Duration:
    4 Years


Where and when

Starts Location
On request
Thapar University P.O Box 32, 147004, Punjab, India
See map
Starts On request
Thapar University P.O Box 32, 147004, Punjab, India
See map

Course programme

First Year: Semester I

Mathematics I
Engineering graphics
Computer Programming
Solid Mechanics
Communication Skills

First year: Semester II

Mathematics II
Manufacturing Process
Electrical and Electronic Science
Organizational Behavior

Second year: Semester I

Numerical and Statistical Methods
Measurement Science and Techniques
Electromagnetic Fields
Semiconductor Devices
Signals and Systems
Digital Electronic Circuits
Human Values, Ethics and IPR

Second year: Semester II

Optimization Techniques
Analog Electronic Circuits
Networks and Transmission Lines
Electrical Engineering Materials
Analog Communication Systems
Data Structure and Information Technology
Environmental Studies

Third year: Semester I

Digital Signal Processing for Communications
VLSI Circuit Design
Digital Communication Systems
Microelectronics Technology
Linear Integrated Circuits and Applications
Summer Training(6 weeks)

Third year: Semester II

Project Semester
Industrial Training(6 weeks)

Fourth year: Semester I

Antenna and Wave Propagation
Modern Control Engineering
Wireless and Mobile Communication Systems
Microwave Engineering
Engineering Economics

Fourth year: Semester II

Optical Communication Systems
Advanced Communication Systems
HDL Based Digital Design
Total Quality Management
Minor Project


Complexity of VLSI chips and trends in IC industry, VLSI design cycle, VLSI Design Flow, Y-Chart: Design abstractions using Behavioral, Structural and Physical domains, role of CAD tools in VLSI Design Automation.

Common algorithmic approaches used in VLSI Design Automation, Greedy methods, Stochastic search, Graph theoritic methods, Dynamic Programming; Optimization Algorithms: Simulated Annealing, Genetic Algorithm and Neural models.

VLSI Physical Design Automation: Algorithms for Partitioning, Floor planning, Placement Routing: Grid Routing, Channel Routing, Global routing, Layout compaction and verification, DRC checks.

Design Verification using Logic Simulation: Compiled code and Event- driven simulation Algorithms, Silicon Compilers

VLSI Design Styles: Standard IC, ASICs

Recent topics in VLSI CAD: Reconfigurable Computing, Embedded System concepts, Hardware Software Co-design, High-Level Synthesis and VHDL modeling.

Laboratory work: Working with layout editor, Implementation of Algorithms used for VLSI Design, logic simulation algorithms, Optimization algorithms- greedy methods, simulated annealing, genetic algorithm and neural models.

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