Diploma in Very Large Scale Integration (VLSI)

Diploma in Very Large Scale Integration (VLSI)

1. ADVANCED DIGITAL DESIGN

* Combinatorial Logic Design
* Sequential Logic Design
* State machines
* Advanced Design Issues Metastability Noise margins
* Power Fan-out
* Design rules Skew Timing considerations

2.1 SYSTEM BUILDING BLOCKS

* Computer Architecture
* Memory Architectures
* Introduction to a system bus (PCI)
* Introduction to a peripheral bus (USB)
* Introduction to LAN (Ethernet)
* Communication Fundamentals Few other topics of Industry relevance

2.2 FPGA ARCHITECTURE

* Architecture study of some popular FPGA families
* Detailed study of a FPGA family
* The Backend tools
* Integrating Non-HDL modules: Building Macros

3. HIGH LEVEL DESIGN METHODOLOGY
DESIGNING WITH HDLS

* V H D L
* Verilog
* Standard coding styles for team Environments

4. HDL SIMULATION AND SYNTHESIS

* The concept of Simulation
* HDL Simulation and Modeling
* The Synthesis Concept
* Synthesis of high level constructs
* Timing Analysis of Logic Circuits
* Combinatorial Logic Synthesis
* State Machine Synthesis
* Efficient Coding Styles
* Hierarchical and flat designs
* Constraining Designs
* Partitioning for Synthesis
* Pipelining
* Resource sharing
* Optimizing arithmetic expressions
* Design reuse The Simulation and Synthesis Tools

5. ASIC DESIGN ISSUES
* ASIC design flow
* Testability: Test principles, fault models, fault coverage, test vectors, test methodologies
* Design for test
* Reliability considerations
* Different technology options
* Power calculations
* Package selection Clock methodologies

6. CMOS VLSI DESIGN

* Introduction to the MOS technology and fabrication process flow
* CMOS combinational logic design
* Design of Basic gates, transmission Gates etc
* Design of complex logic
* Device sizing, timing parameters and Estimation of layout resistance and Capacitance
* Design rules for CMOS layout
* Introduction to layout and simulation tools
* Place and Route Extraction, LVS
* Net list to GDS-II flow
* Device Generator Libraries

7. PROJECTS

* Industry standard projects
* Documentation
* Architecture design
* HDL description, simulation, synthesis
* FPGA implementation
* Post-layout simulation

8. Verification using SystemVerilog 36 hrs

* Introduction to Verification
* Types of verification
* Code coverage Introduction to SystemVerilog
* Introduction to task & functions in SystemVerilog
* OOPs Terminology
* Implementation of OOPs Concepts in SystemVerilog
* Randomization
* Case Studies
* Assertions property
* Assertions Time
* Functional Coverage

9. Linux Shell Scripting 10 Hrs

* Linux Commands
* Linux File System
* Vi editor
* The Shell
* Shell Programming