M.E. Electronics & Comm. Engg:ASICs and FPGAs
Master
In Patiala
Description
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Type
Master
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Location
Patiala
Facilities
Location
Start date
Start date
Reviews
Course programme
First Semester
Advanced Digital signal Processing
Advanced Optical Communication Systems
Research Methodology
Digital VLSI Design
Microelectronics Technology
Second Semester
Advanced Solid State Devices
Advanced Communication Techniques
Hardware Description Languages
Third Semester
CDMA and GSM Systems
Seminar
Thesis (starts)
Fourth Semester
Thesis
ASICs and FPGAs
Introduction: course outline, logistics introduction to ASICs, FPGAs, economics
HDL: Logic design Review, Behavior, dataflow, structural modeling, control statements, FSM modeling
CMOS Review: Classical, CMOS (Deep Sub-micron), ASIC Methodologies (classical) ASIC Methodologies (aggressive)
Fabrication of MOSFET: MOS Transistor, Design methodologies, design for manufacturability and testability.
FPGA: Programmable logic FPGA, Configuration logic blocks, Function Generator, ROM implementation, RAM implementation, time skew buffers, FPGA Design tools, Network-on-chip, Adaptive System-on-chip, AES ASIC Implementation, Advanced FPGA Design
Logic synthesis: Fundamentals, logic synthesis with synopsis, physical design compilation, simulation, implementation. ? Floor planning and placement, Commercial EDA tools for synthesis.
Testing: Advanced interconnects and testing techniques
M.E. Electronics & Comm. Engg:ASICs and FPGAs