M.E. Electronics & Comm. Engg:Computer Architecture

Thapar University
In Patiala

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Important information

  • Master
  • Patiala
Description

Important information
Venues

Where and when

Starts Location
On request
Patiala
Thapar University P.O Box 32, 147004, Punjab, India
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Course programme

First Semester

Advanced Digital signal Processing
Advanced Optical Communication Systems
Research Methodology
Digital VLSI Design
Microelectronics Technology

Second Semester

Advanced Solid State Devices
Advanced Communication Techniques
Hardware Description Languages


Third Semester

CDMA and GSM Systems
Seminar
Thesis (starts)


Fourth Semester

Thesis


Computer Architecture

Overview of von Neumann architecture: Instruction set architecture; The Arithmetic and Logic Unit, The Control Unit, Memory and I/O devices and their interfacing to the CPU; Measuring and reporting performance; CISC and RISC processors.

Pipelining: Basic concepts of pipelining, data hazards, control hazards, and structural hazards; Techniques for overcoming or reducing the effects of various hazards.

Hierarchical Memory Technology: Inclusion, Coherence and locality properties; Cache memory organizations, Techniques for reducing cache misses; Virtual memory organization, mapping and management techniques, memory replacement policies.

Instruction-level Parallelism: Concepts of instruction-level parallelism (ILP), Techniques for increasing ILP; Superscalar, superpipelined and VLIW processor architectures; Vector and symbolic processors; Case studies of contemporary microprocessors

Multiprocessor Architecture: Taxonomy of parallel architectures; Centralized shared-memory architecture, synchronization, memory consistency, interconnection networks; Distributed shared-memory architecture, Cluster computers.

Non von Neumann Architectures: Data flow Computers, Reduction computer architectures, Systolic Architectures.


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