M.Tech. VLSI Design & CAD:CAD for VLSI

Thapar University
In Patiala

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Important information

  • Master
  • Patiala
Description

Important information
Venues

Where and when

Starts Location
On request
Patiala
Thapar University P.O Box 32, 147004, Punjab, India
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Course programme

First Semester I

Physics of Semiconductor Devices
IC Fabrication Technology
Digital VLSI Design
CAD Systems Environment
Research Methodology


Second Semester

Analog IC Design
Hardware Description Languages
Embedded Systems


Third Semester

Seminar
Thesis starts

Fourth Semester

Thesis


CAD for VLSI

`Introduction to VLSI design methodologies and supporting CAD environment.

Schematic editors: Parsing: Reading files, describing data formats, Graphics & Plotting Layout. Layout Editor: Turning plotter into an editor. Layout language: Parameterized cells, PLA generators, Introduction to Silicon compiler, Datapath. Compiler, Placement & routing, Floor planning.

Layout Analysis: Design rules, Object based DRC, Edge based layout operations. Module generators.

Simulation: Types of simulation, Behavioral simulator, logic simulator, functional simulator & Circuit simulator.

Simulation Algorithms: Compiled code and Event-driven. Optimization Algorithms: Greedy methods, simulated annealing, genetic algorithm and neural models.

Testing ICs: Fault simulation, Aids for test generation and testing. Computational complexity issues: Big Oh and big omega terms.

Recent topics in CAD-VLSI: Array compilers, hardware software co-design, high-level synthesis tools and VHDL modeling.


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