M.Tech. VLSI Design & CAD:Fault – Tolerance in VLSI

Thapar University
In Patiala

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Important information

  • Master
  • Patiala
Description

Important information
Venues

Where and when

Starts Location
On request
Patiala
Thapar University P.O Box 32, 147004, Punjab, India
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Course programme

First Semester I

Physics of Semiconductor Devices
IC Fabrication Technology
Digital VLSI Design
CAD Systems Environment
Research Methodology


Second Semester

Analog IC Design
Hardware Description Languages
Embedded Systems


Third Semester

Seminar
Thesis starts

Fourth Semester

Thesis


Fault – Tolerance in VLSI

Motivation of fault tolerance in arithmetic systems. Fault and error models in VLSI arithmetic units. Reliability and fault tolerance definitions. Reliability and availability modeling,

Estimation of the reliability and availability of fault tolerant systems Fault diagnosis. Fault tolerance measurement. Fault tolerance strategies: detection, correction, localization, reconfiguration. Error recovery, Error detecting and correcting codes

Detection/correction techniques: modular redundancy, time redundancy (e.g., RESO, RERO, REDWC, RETWV, REXO), datacoding (e.g., AN codes, residue codes, gAN codes, RBR codes, Berger codes, residue number systems), algorithm-based techniques. Reconfiguration techniques.

Applications to arithmetic units and systems (e.g., convolvers, inner product units, FFT units, neural networks). Application levels: unit, processing element, subsystem, system. Cost/benefit analysis. Fault-tolerant transaction processing systems. Fault-tolerant Networks. Redundant disks (RAID).

Software reliability models, Software fault-tolerance methods: N-version programming, recovery blocks, rollback and recovery

Architecture and design of fault tolerant computer systems using protective redundancy
First Semester I

Physics of Semiconductor Devices
IC Fabrication Technology
Digital VLSI Design
CAD Systems Environment
Research Methodology


Second Semester

Analog IC Design
Hardware Description Languages
Embedded Systems


Third Semester

Seminar
Thesis starts

Fourth Semester

Thesis


Fault – Tolerance in VLSI

Motivation of fault tolerance in arithmetic systems. Fault and error models in VLSI arithmetic units. Reliability and fault tolerance definitions. Reliability and availability modeling,

Estimation of the reliability and availability of fault tolerant systems Fault diagnosis. Fault tolerance measurement. Fault tolerance strategies: detection, correction, localization, reconfiguration. Error recovery, Error detecting and correcting codes

Detection/correction techniques: modular redundancy, time redundancy (e.g., RESO, RERO, REDWC, RETWV, REXO), datacoding (e.g., AN codes, residue codes, gAN codes, RBR codes, Berger codes, residue number systems), algorithm-based techniques. Reconfiguration techniques.

Applications to arithmetic units and systems (e.g., convolvers, inner product units, FFT units, neural networks). Application levels: unit, processing element, subsystem, system. Cost/benefit analysis. Fault-tolerant transaction processing systems. Fault-tolerant Networks. Redundant disks (RAID).

Software reliability models, Software fault-tolerance methods: N-version programming, recovery blocks, rollback and recovery

Architecture and design of fault tolerant computer systems using protective redundancy


Compare this course with other similar courses
See all