M.Tech. VLSI Design & CAD:High Level Synthesis
Master
In Patiala
Description
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Type
Master
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Location
Patiala
Facilities
Location
Start date
Start date
Reviews
Course programme
First Semester I
Physics of Semiconductor Devices
IC Fabrication Technology
Digital VLSI Design
CAD Systems Environment
Research Methodology
Second Semester
Analog IC Design
Hardware Description Languages
Embedded Systems
Third Semester
Seminar
Thesis starts
Fourth Semester
Thesis
High Level Synthesis
Introduction: Level of Abstraction, Need for Design Automation on Higher Abstraction Levels, Essentiel issues in Synthesis.
Architectural Models in Synthesis. Combinational Logic, Finite State Machines.
Quality Measures: Area and Performance measures, Other Measures.
Design Description Language: HDLs, Hardware Specific Features, Formats, HDLs for DSP, Simulation Based HDLs, Modeling Guidelines for HDLs
Design Representation and Transformations:
Partitioning.
Scheduling.
Allocation.
Design Methodology for High-Level Synthesis: Generic Synthesis, System Synthesis, Chip Synthesis, Logic and Sequential Synthesis, Physical-Design Methodology, System and component Databases, Conceptualization Environment.
High Level Synthesis of ASICs.
High-Level Synthesis for Real-Time Digital Signal Processing.
M.Tech. VLSI Design & CAD:High Level Synthesis