M.Tech. VLSI Design & CAD:VLSI Digital Signal Processing

Thapar University
In Patiala

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Important information

  • Master
  • Patiala
Description

Important information
Venues

Where and when

Starts Location
On request
Patiala
Thapar University P.O Box 32, 147004, Punjab, India
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Course programme


First Semester I

Physics of Semiconductor Devices
IC Fabrication Technology
Digital VLSI Design
CAD Systems Environment
Research Methodology


Second Semester

Analog IC Design
Hardware Description Languages
Embedded Systems


Third Semester

Seminar
Thesis starts

Fourth Semester

Thesis

VLSI Digital Signal Processing

Introduction to Digital Signal Processing Systems: Introduction, typical DSP Algorithms, DSP Application demands and scaled CMOS technologies, Representation of DSP Algorithms.

Iteration Bound: Introduction, Data Flow Graph Representations, Loop Bound and Iteration Bound, Algorithms for computing iteration bound, Iteration bound of multirate data flow graphs.

Pipelining and Parallel Processing: Introduction, Pipelining of FIR Digital Filters, Parallel Processing, Pipelining and Parallel Processing for low power.

Retiming and Unfolding: Introduction, Definations and properties, Solving systems of inequalities, Retiming Techniques, An algorithm for unfolding, Critical path, Unfolding and retiming, Applications of unfolding

Folding: Introduction, folding techniques, register minimization techniques, register minimization in folded architecture, folding of multirate systems

Systolic Architecture Design: Introduction, ystem array design methodology, FIR systolic arrays, selection of scheduling vector, matrix-matrix multiplication and 2-D systolic array design, Systolic Design for space representations containing delays.

Instruction Set: Instruction types, various types registers, orthogonality, assembly language and application development.

Processors: Architecture and instruction set of TMS320C3X, TMS320C5X, TMS320C6X, ADSP 21XX DSP Chips, some example programs. Fast Convolution: Introduction cook-Toom algorithm, Winograd algorithm, iterated convolution, Cyclic convolution, Design of fast convolution algorithm by inspection Algorithmic Strength reduction in filter and transforms:

Introduction, parallel FIR Filters, discrete cosine transform and inverse DCT, parallel architectures for Rank Order filters.

Pipelined and Parallel Recursive and Adaptive filters: Introduction, pipeline interleaving in digital filters, pipelining in 1st order IIR digital filters, pipelining in higher order IIR digital filters, parallel processing for IIR filters, combined pipelining and parallel processing for IIR filters, low power IIR Filter Design using pipelining and parallel processing, pipelined adaptive digital filters.

Recent Trends in DSP System Design: FPGA-Based DSP System Design, advanced development tools for FPGA, Development tools for Programmable DSPs ?V an introduction to Code Composer Studio.


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