M.Tech. VLSI Design & CAD:VLSI Subsystem Design
Master
In Patiala
Description
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Type
Master
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Location
Patiala
Facilities
Location
Start date
Start date
Reviews
Course programme
First Semester I
Physics of Semiconductor Devices
IC Fabrication Technology
Digital VLSI Design
CAD Systems Environment
Research Methodology
Second Semester
Analog IC Design
Hardware Description Languages
Embedded Systems
Third Semester
Seminar
Thesis starts
Fourth Semester
Thesis
VLSI Subsystem Design
Review of Transistor, Inverter Analysis, CMOS Process and Masking Sequence, Layer Properties and Parasitic Estimation.
VLSI Design Flow, Design Methodologies, Abstraction Levels.
Design of Data Processing Elements: Adder Architectures, Multiplier Architectures, Counter Architectures, ALU Architectures, Design of Storage Elements: Latches, Flip-Flops, Registers, Register Files.
Design of Control Part: Moore & Mealy Machines, PLA Based Implementation, Random Logic Implementation, Micro-programmed Implementation.
Structuring of Logic Design: PLA Design, PLA Architectures, Gates Array Cell Design, Concept of Standard Cell Based Design, Cell Library Design.
Memory Design: SRAM cell, Various DRAM cells, RAM Architectures, Address Decoding, Read/Write Circuitry, Sense Amplifier and their Design, ROM Design.
Clocking Strategies, Clock Skew, Clock Distribution and Routing, Clock Buffering, Clock Domains, Gated Clock, Clock Tree.
Synchronization Failure and Meta-stability.
M.Tech. VLSI Design & CAD:VLSI Subsystem Design