M.Tech. VLSI Design & CAD:VLSI Testing and Design for Testability

Master

In Patiala

Price on request

Description

  • Type

    Master

  • Location

    Patiala

Facilities

Location

Start date

Patiala (Punjab)
See map
Thapar University P.O Box 32, 147004

Start date

On request

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Course programme


First Semester I

Physics of Semiconductor Devices
IC Fabrication Technology
Digital VLSI Design
CAD Systems Environment
Research Methodology


Second Semester

Analog IC Design
Hardware Description Languages
Embedded Systems


Third Semester

Seminar
Thesis starts

Fourth Semester

Thesis


VLSI Testing and Design for Testability

Physical defects and their modeling; stuck at faults; Bridging Faults; Fault collapsing.

Fault Simulation: Deductive, Parallel and Concurrent; Critical Path Tracing.

Test Generation for Combinational Circuits: D-Algorithm, Boolean Difference, PODEM, and ATPG.

Random, Exhaustive and Weighted Random Test Pattern Generations Aliasing and its effect on Fault coverage.

PLA Testing: cross-point Fault Model, Test Generation,

Memory testing: Permanent Intermittent and Pattern Sensitive Faults; Delay Faults and Hazards; Test Generation Techniques;

Test Generation for Sequential Circuits.

Scan Design. Scan path and LSSD, BILBO,

Concept of Redundancy, spatial redundancy, Time redundancy

Recent trends in VLSI testing: Genetic Algorithms, Parallel Algorithms, Neural networks, nano scale testing.

M.Tech. VLSI Design & CAD:VLSI Testing and Design for Testability

Price on request