Training in VLSI

1. Preface to Graphic Editor plus PLD
2. H.D.L. V.H.D.L. Design Entity,
3. Data-Objects
4. Statements of Signal Assignments
5. Simultaneous Signal Assignments
6. Conditional Signal Assignments
7. Chosen Signal Assignment
8. Chronological Procedure
9. IF, CASE, Using VARIABLE in Process
10. Using a Process for a Combinational Circuit
11. Packages and Use Clauses
12. Components
13. Sequential Circuits
14. Gated D Latch D,JK, T Flip Flop with CLR
15. PRN, ENB Using WAIT UNTIL Statement
16. Flip Flops with Asynchronous / Synchro nous Load
17. Array of Flip – Flops
18. Instantiating a Flip Flop from a Library
19. Up/Down Counter
20. Synchronous clear
21. load, allow Counter
22. Modulus 200 up counter
23. Shift Registers(4 – Bit)
24. Subprograms, Procedures, Functions
25. Clock Configuration Guidelines
26. Meta-stability
27. Projects executed on an actual F.P.G.A. throughout the program
28. Mux(“2:1”, “4:1”, “8:1”, “16:1”)
29. Encoder(4:2, 8:3), Decoder(2:4, 3:8), Priority Encoder(4:2, 8:3)
30. Half Adder / Full Adder / 4 – bit Adder
31. Comparator(1 – Bit, 4 – Bit)
32. Counter, Shift Register, Parametric Design – Generic plus Generate Statement
33. Use of internal memory - Dual Port / Single Port ROM / RAM
34. Synchronous/Asynchronous
35. Multidimensional Array - Constrained & Unconstrained
36. Resolution Functioning for unimpeded multi-dimensional arrays
37. Multichip projects plus Simulations
38. Design of User Defined Functions
39. Testbenches, Text I / O
40. Attributes, Configure, Packaged Bodies
41. Function Over-loading
42. Projects executed on an definite F.P.G.A. through the Program Parametric designs of Mux, Encoder, Decoder, Priority-Encoder, Half-Adder/ Full Adder / 4-bit Adder
43. Comparator, Counters, Shift-Register