MS VSDV (VLSI)

Manipal University
In Manipal

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Important information

  • Master
  • Manipal
  • Duration:
    2 Years
Description

Important information
Venues

Where and when

Starts Location
On request
Manipal
IV Floor, Innovation Centre, MIT Campus, Manipal, 576104, Karnataka, India
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Course programme

Manipal University in association with Axiom Design Automation, Bangalore (One of the leading EDA Solution provider) offers four semester postgraduate course in “VLSI System Design & Verification” to address current emerging technologies. The MS programme is a step towards making technical learning very practical and relevant.

Semester I

Digital Systems Design
Verification & Scripting

Linux & Data Structures
Digital Systems Design Lab
Seminar - I
Project – I

Semester II

Elective
Elective Lab
Seminar - II
Project -II

III & IV SEMESTER

Project Work

Electives
Advanced VLSI Design
Physical Design
Signal Processing


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