B.E. Computer Science & Engineering:VLSI CAD
Bachelor
In Patiala
Description
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Type
Bachelor
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Location
Patiala
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Duration
4 Years
Facilities
Location
Start date
Start date
Reviews
Course programme
First Year: Semester I
Mathematics I
Engineering graphics
Computer Programming
Physics
Solid Mechanics
Communication Skill
First Year: Semester-II
Mathematics II
Manufacturing Process
Chemistry
Electrical and Electronic Science
Thermodynamics
Organizational Behavior
Second Year- Semester - I
Measurement Science and Techniques
Optimization Techniques
Semiconductor Devices
Data Structures
Discrete Mathematical Structures
Digital Electronic Circuits
Human Values, Ethics and IPR
Second Year- Semester – II
Numerical and Statistical Methods
Electrical Engineering Materials
Computer System Architecture
Principles of Programming Languages
Analysis and Design of Information Systems
Operating Systems
Environmental Studies
Third Year- Semester – I
Object Oriented Programming
Theory of Computation
Computer Networks
Data Base Management Systems
Software Engineering
Microprocessors
Summer Training
Third Year- Semester – II
Total Quality Management
Algorithm Analysis and Design
Software Project Management
Internet and Web Technologies
Fourth Year- Semester – I
Engineering Economics
System Software
Compiler Construction
Computer Graphics
Artificial Intelligence
Fourth Year- Semester – II
Project Semester
Project
Industrial Training(6 weeks)
VLSI CAD
Complexity of VLSI chips and trends in IC industry, VLSI design cycle, VLSI Design Flow, Y-Chart: Design abstractions using Behavioral, Structural and Physical domains, role of CAD tools in VLSI Design Automation.
Common algorithmic approaches used in VLSI Design Automation, Greedy methods, Stochastic search, Graph theoritic methods, Dynamic Programming; Optimization Algorithms: Simulated Annealing, Genetic Algorithm and Neural models.
VLSI Physical Design Automation: Algorithms for Partitioning, Floor planning, Placement Routing: Grid Routing, Channel Routing, Global routing, Layout compaction and verification, DRC checks.
Design Verification using Logic Simulation: Compiled code and Event- driven simulation Algorithms, Silicon Compilers
VLSI Design Styles: Standard IC, ASICs
Recent topics in VLSI CAD: Reconfigurable Computing, Embedded System concepts, Hardware Software Co-design, High-Level Synthesis and VHDL modeling.
Laboratory work: Working with layout editor, Implementation of Algorithms used for VLSI Design, logic simulation algorithms, Optimization algorithms- greedy methods, simulated annealing, genetic algorithm and neural models.
B.E. Computer Science & Engineering:VLSI CAD