B.E. Electronics & Comm. Engg:DSP Processors

Thapar University
In Patiala

Price on request
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Important information

Typology Bachelor
Location Patiala
Duration 4 Years
  • Bachelor
  • Patiala
  • Duration:
    4 Years


Where and when

Starts Location
On request
Thapar University P.O Box 32, 147004, Punjab, India
See map
Starts On request
Thapar University P.O Box 32, 147004, Punjab, India
See map

Course programme

First Year: Semester I

Mathematics I
Engineering graphics
Computer Programming
Solid Mechanics
Communication Skills

First year: Semester II

Mathematics II
Manufacturing Process
Electrical and Electronic Science
Organizational Behavior

Second year: Semester I

Numerical and Statistical Methods
Measurement Science and Techniques
Electromagnetic Fields
Semiconductor Devices
Signals and Systems
Digital Electronic Circuits
Human Values, Ethics and IPR

Second year: Semester II

Optimization Techniques
Analog Electronic Circuits
Networks and Transmission Lines
Electrical Engineering Materials
Analog Communication Systems
Data Structure and Information Technology
Environmental Studies

Third year: Semester I

Digital Signal Processing for Communications
VLSI Circuit Design
Digital Communication Systems
Microelectronics Technology
Linear Integrated Circuits and Applications
Summer Training(6 weeks)

Third year: Semester II

Project Semester
Industrial Training(6 weeks)

Fourth year: Semester I

Antenna and Wave Propagation
Modern Control Engineering
Wireless and Mobile Communication Systems
Microwave Engineering
Engineering Economics

Fourth year: Semester II

Optical Communication Systems
Advanced Communication Systems
HDL Based Digital Design
Total Quality Management
Minor Project

DSP Processors

An Introduction to DSP Processors: Advantages of DSP, characteristics of DSP systems, classes of DSP applications, DSP processor embodiment and alternatives, Fixed Vs Floating point processors, fixed point and Floating point Data Paths.

DSP Architecture: An introduction to Harvard Architecture, Differentiation between Von-Neumann and Harvard Architecture, Quantization and finite word length effects, Bus Structure, Central Processing Unit � ALU, Accumulators, Barrel Shifters, MAC unit, compare, select, and store unit (CSSU), data addressing and program memory addressing.

Memory Architecture: Memory structures, features for reducing memory access required, wait states, external memory interfaces, memory mapping � data memory, program memory and I/O memory, memory mapped registers.

Addressing: Various addressing modes - implied addressing, immediate data addressing, memory direct addressing, register direct and indirect addressing, and short addressing modes.

Instruction Set: Instruction types, various types registers, orthogonality, assembly language and application development.

Execution Control and Pipelining: Hardware looping, interrupts, stacks, pipelining and performance, pipelining depth, interlocking, branching effects, interrupt effects, instruction pipelining.

Peripherals: Serial ports, timers, parallel ports, bit I/O port, host ports, communication ports, on-chip A/D and D/A converters, external interrupts, on chip debugging facilities, power consumption and management.

Processors: Architecture and instruction set of TMS320C3X, TMS320C5X, TMS320C6X, ADSP 21XX DSP Chips, some example programs.

Recent Trends in DSP System Design: FPGA-Based DSP System Design, advanced development tools for FPGA, Development tools for Programmable DSPs � an introduction to Code Composer Studio.

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