M.Tech. VLSI Design & CAD:Low Power CMOS Design

Master

In Patiala

Price on request

Description

  • Type

    Master

  • Location

    Patiala

Facilities

Location

Start date

Patiala (Punjab)
See map
Thapar University P.O Box 32, 147004

Start date

On request

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Course programme

First Semester I

Physics of Semiconductor Devices
IC Fabrication Technology
Digital VLSI Design
CAD Systems Environment
Research Methodology


Second Semester

Analog IC Design
Hardware Description Languages
Embedded Systems


Third Semester

Seminar
Thesis starts

Fourth Semester

Thesis


Low Power CMOS Design

Low Power Microelectronics: Retrospect and Prospect, Fundamentals of power dissipation in microelectronic devices, Estimation of power dissipation due to switching, short circuit, sub-threshold leakage, and diode leakage currents.

CMOS Scaling: Scaling for High Performance and Low-Power. Low Voltage Technologies and Circuits: Threshold Voltage Scaling and Control, Multiple Threshold CMOS (MTCMOS), Substrate Bias Controlled Variable Threshold CMOS. Testing Issues: Design and test of low-voltage CMOS circuits.

Circuit And Logic Styles: Power-conscious logic Styles, Adiabatic Logic Circuits. Power Analysis and optimization: Power Analysis Techniques, Power Optimization Techniques, Energy recovery techniques, Software power estimation and optimization Low-Power Memory Circuits and architectures.

Power Conscious high-level synthesis Silicon-on-Insulator Based Technologies.

M.Tech. VLSI Design & CAD:Low Power CMOS Design

Price on request