M.Tech. VLSI Design & CAD:VLSI Architectures
Master
In Patiala
Description
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Type
Master
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Location
Patiala
Facilities
Location
Start date
Start date
Reviews
Course programme
First Semester I
Physics of Semiconductor Devices
IC Fabrication Technology
Digital VLSI Design
CAD Systems Environment
Research Methodology
Second Semester
Analog IC Design
Hardware Description Languages
Embedded Systems
Third Semester
Seminar
Thesis starts
Fourth Semester
Thesis
VLSI Architectures
Complex Instruction Set Computers (CISC): Instruction Set, Characteristics and Functions, Addressing Modes, Instruction Formats, Architectural Overview, Processor Organization, Register Organization, Instruction Cycle, Instruction Pipelining, Pentium Processor, PowerPC Processor.
Reduced Instruction Set Computers (RISC): Instruction execution Characteristics, Register Organization, Reduced Instruction Set, Addressing Modes, Instruction Formats, Architectural Overview, RISC Pipelining, Motorola 88510, MIPS R4650, RISC Vs. CISC.
DSP Processors: Instruction Set, Addressing Modes, Instruction Formats, Architectural Overview.
Pipeline Processing: Basic Concepts, Classification of Pipeline Processors, Instruction and Arithmetic Pipelining: Design of Pipelined Instruction Units, Pipelining Hazards and Scheduling, Principles of Designing Pipelined Processors.
Superscaler Processors: Overview, Design Issues, PowerPC, Pentium.
M.Tech. VLSI Design & CAD:VLSI Architectures