Master of Technology (VLSI Design)

Laxmi Devi Institute of Engineering & Technology
In Alwar

Price on request
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Important information

Typology Master
Location Alwar
  • Master
  • Alwar

Where and when
Starts Location
On request
Alwar-tijara-delhi Highway Chikani Alwar, 301028, Rajasthan, India
See map
Starts On request
Alwar-tijara-delhi Highway Chikani Alwar, 301028, Rajasthan, India
See map

Course programme

Engineering Mathematics – I
Physics / Engg. Chemistry
Computer Systems & Prog.
Electrical & Electronics Engineering
Physics / Engg. Chem. Lab
Computer Programming Lab
Practical Geometry
Workshop Practice
Electrical & Electronics Lab
Discipline & Extracurricular Activities
Communication Techniques
Engineering Mathematics – II
Physics / Engg. Chemistry
Engineering Mechanics
Language Lab
Physics / Chemistry Lab
Environmental Engg. Lab
Machine Drawing
Discipline & Extra Curricular Activities
Optimization problem-Convex sets and functions.
The SIMPLEX Algorithm- Forms of linear programming problem, geometry of linear programming,
Organization of Tableau. Computational considerations for SIMPLEX Algorithm.
Duality: Dual of linear programming, dual simplex problem, Primal-dual algorithm.
Algorithms and Complexity-shortest path, max-flow, Dijkstra’s algorithm, min-cost flow, algorithm for graph
search and matching; spanning trees and matroids; Integer Linear programming, Greedy algorithm,
approximation algorithms; branch-and-bound; dynamic programming.

Basic operation of CMOS inverter, detailed analysis of its noise margin propagation delay, power
dissipation concept of layout & area, layout optimization & area estimation for a single as well as
combinational logic circuits.
Design of sequential logic circuits: Static & dynamic latches registers, dynamic transmission gate, CMOS
gate, pipelining approach for optimize sequential circuits, NDRA-CMOS pipelined structure, non-bistable
sequential circuits, Schmitt trigger.
Implementation strategies for digital ICs, introduction of custom and circuit design, hierarchy cell based
design array based implementation, building blocks of adder, multiplier, shifter, barrel shifter, algorithmic
shifter and other arithmetic operators, power speed tradeoff in data path structure.
Design memory & array structure memory architectures & building blocks, address decoder, sense
amplifiers, driver/ buffers, timing control, power dissipation in memories, idea of testability and fault
detection models.

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